1. Field of the Invention
The present invention relates to electrically data rewritable non-volatile semiconductor memory devices.
2. Description of the Related Art
Conventionally, nonvolatile semiconductor memory devices capable of electrically rewriting data, such as electrically erasable programmable read-only memory (EEPROM), are known as one type of semiconductor memories. Among them, an EEPROM of the NAND type having a NAND cell attracts the attention of technicians as the one that can be highly integrated. The NAND cell is arranged by series connection of a plurality of memory cells, each of which is a unit for storing 1 bit of data. The NAND type EEPROM is adaptable for use as a memory card for storing image data of digital still cameras, by way of example.
Memory cells of a NAND-EEPROM has an FET-MOS structure in which a floating gate (charge accumulation layer) and a control gate are stacked or multilayered above a channel region of a semiconductor substrate, with a dielectric film interposed therebetween. The control gate is connected to a word line. A NAND cell is configured from a plurality of memory cells which are connected in series together in the form that a source/drain is commonly used or “shared” by neighboring ones of the plurality of cells. The source/drain as used herein refers to an impurity-doped region which functions as at least either one of the source and drain of a transistor.
Here, one example of a data write or “programming” scheme in the NAND type chip will be explained in brief.
(1) “0” Write
In a state that the voltage of a channel region is set at 0V, select a word line of a memory cell into which a logic “0” is to be written; then, set the voltage of this word line at 20V for example, and set the word lines other than this word line at 10V for instance. As a potential difference between the selected word line (control gate) and the channel region is significant large, electrons are injected into the floating gate of the above-noted memory cell in the form of a tunnel current. Whereby, the memory cell comes to have its threshold voltage which is set in a positive state (“0”-written state).
(2) “1” Write
After having set the channel region in a floating state with a prespecified voltage higher than or equal to 0V, select the word line of a memory cell into which a logic “1” is to be written and then set the voltage of this word line at 20V in a similar way to the case of “0” write. Set the voltages of those word lines other than this word line at 10V for example. With these voltage settings, the channel region increases in potential due to the presence of a capacitive coupling with respect to the selected word line (control gate); for example, it potentially rises up to approximately 8V. In this case, unlike the case of “0” write, the potential difference between the selected word line (control gate) and the channel stays less so that the floating gate of the “1”-written memory cell hardly experiences any electron injection due to the flow of a tunnel current. Accordingly, the threshold voltage of the above-noted memory cell is kept in a negative state (“1” written state).
In another example of the write scheme of NAND-EEPROM, writing is done while setting at 0V the word lines of memory cells that are respectively located next to the both neighboring memory cells of a selected memory cell, in order to preclude or avoid erroneous writing to a memory cell (for example, see FIG. 10(b) of Published Japanese Patent Application No. 2002-260390).